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PCB (Printed Circuit Board) Planning and Routing Tips and Tactics


first Introduction

PCB Printed Circuit Board. PCBs are part of our daily lives; Computers, mobile phones, calculators, watches and all the electrical parts we are in daily contact with.

This article is for professionals who are familiar with hardware design and have a PCB design background.

2. Formatting the PCB

The most common form of PCB is rectangle. Many also want the corners to be rounded, as this determines the possibility of flipping. The shape of the PCB is highly dependent on where the plate is placed and the mechanical requirements (the last box where the product is placed).

Usually there are 4 big holes on the board, every hole in one corner. These holes are used to hold the sheet in place with a patch or a PCB holder. The diameter is greater than 2 mm and is fitted.

3. How many layers can be used?

Now we get to the next step, how many layers do we use? This depends to a large extent on the maximum frequency used in the design, how many components it is, whether or not the components of Ball-Grid-Array are, and most importantly, the design.

For systems up to 80 MHz, it is usually necessary to use 2 layers if it is possible that the board can be made to do so. Observe the CE certificate and the FCC rules. In most cases, up to -130 dBm emissions are required in the public radio band (FM 80-108MHz). This can be a problem if you use a high current clock between 40 and 80 MHz (the second harmonic would be between 80 and 160 MHz, which could easily damage these rules).

For systems above 80MHz, it is very important to use multiple layers (4 good examples).

There are 2 tactics in 4 layers:

  1. The top and bottom layers can be Earth and Power. The middle layers used for routing.
  2. The upper and lower layers used for the signal, the middle layers used in the planes

The first method has a very good signal quality because the signals are arranged between two power supplies and as a result you will have minimal emissions.

The second method may facilitate routing because it will not be necessary for each needle (vertical linkage), since the needle is located on the same marker layer. In addition, the internal planes may have more islands to cover all energy requirements and thus further reduce the transmission number. But this method can be very complicated and

it is very important not to interrupt the performance projects under high-speed signals, as this can lead to a return path loop the undesirable emission is more likely . .

Using multiple layers always results in better product quality, but makes development more costly, especially at the prototype stage of production. (The difference between the 2-layer prototype and the 4-6 layer can be as much as a few hundred dollars).

The six-layer method is almost ideal. The use of top and bottom layers, such as routing and inner layers, to prevent routing may prevent emissions, increase noise resistance, and drastically reduce design effort, as multiple layers can be used for routing. The impedance fit can be easily accomplished and covered with high speed signals.

4. Arrangement of Layers for Impedance Matching

At this moment I assume that you are dealing with a high-speed system that has SSTL, HSTL, LVDS, RSDS, GTL +, high-speed TTL and other high-speed connections (USB HS, 2.5Gbps PCI-Express etc.). These routes require special considerations. Lines require impedance matching. For many beginners this may be a questionnaire. The difference between impedance and resistance is high. If you need resistance, you can easily use a resistor and do so.

In contrast, impedance matching has nothing to do with resistors. It depends on the width of the bar, the plane of the bottom side, be it the Strip-Line (about two nourishing planes) or the uStrip (which means there is a power machine on it, but the other side is free like the TopLayer) Egypt BottomLayer) .

To achieve a certain impedance on a track, carefully select these parameters. The desired impedance (usually 50 or 75 ohms) can be found by using the impedance calculator (search google) for the appropriate width, height and thickness of the metallic layer.

Please note that there is a missing impedance relationship (especially RF, high-speed USB, SATA or PCI-Express, and memory lines such as SSTL or HSTL) and for obvious reasons. This forces you to go to the next prototype without ever knowing what caused the first prototype.

5. Energy Management

One of the most important factors in high-speed digital design is energy islands. The FPGA or high-speed processor board that accurately designs performance can be very unstable. In the early days, a slightly wider range of paths can be transmitted than the signal bands and treated as normal connections. Today the story is different.

If you are using FPGAs or high-speed processors, you need to know that the large number of flip flops will change at any moment in the system. Switching results in huge amounts of power through the power and grounding pins. In this case, the soil pins can create a ground jump if the current (and especially the speed) is high. I have to remind you of the famous V = L. di / dt (Delta voltage equals the current x inductance speed). If you use a track (for example) to control ground signals, there will be different voltages on both sides of the track. It will be very funny if you have + 0.5V on one side of the earth and -1V on the other side.

This is a COMPLETE SYSTEM error. I remember experiencing this problem in the early days, which forced me to question even the basic physical rules. Finding this error can be difficult, and even if we discover it, there will be no choice but to create another prototype.

The same rule applies to both. You can easily fall into certain bands if you don't use planes or high-power islands to support the voltage. The use of a larger number of disconnect capacitors is recommended for high speed and high performance processors / FPGAs near power lines.

The RF section and power switching stages require special care for their ground planes. Their islands must be separated from the kernel plane and connected to lanes that connect the switching island to the kernel (the tracks must be large enough to provide nearly zero DC resistance, but not more). This is because shifting and the RF section can create waves in the ground plane that can jump to the ground. If you would like further explanation, please visit Google on this topic.

6. High Speed ​​Differential Signals

Today's designs always have high speed differential connections. Examples are PCI-Express, high-speed USB and SATA. Some rules apply to these lines:

  1. No ground level should be distributed between such lines.
  2. Their impedance must be carefully coordinated.
  3. There must be no more than 2 millimeters of difference at LENGTH for each connection.
  4. Relationships must keep the same distance between each other until they reach the destination.
  5. No sharp corners. Avoid 45 degrees or 90 degrees. This can cause unwanted capacitive coupling or cause a small antenna.
  6. Keep all other signals on these lines away. I recommend a separation of at least 5 mm. This reduces conversation.

For such connections, I recommend using Strip lines. But again, many Micro-Strips will work well.

7th High Speed ​​Single End Connections

Managing High Speed ​​Single End Connections can be challenging. Because they are not differential lines, the noise on these lines will affect their condition and cause system errors. HSTL, SSTL and GTL + are good examples. LVTTL should also be treated.

When guiding these lines, consider these tips:

  1. The impedance matching for these connections is BLACK.
  2. There are no pieces of land on these relationships.
  3. Cross-talk should be minimized. This depends largely on the type of connection. LVTTL is most prone to cross-talk because they do not have end-resistors. If possible, we recommend using SSTL or HSTL.
  4. Exact lines should be kept away from busy connections. These lines are typically control lines, and any cross-talk can be catastrophic (Imagine talking through chat choice!).
  5. The sharp corners of these signals are okay, as they usually operate at 800 MHz.
  6. Reducing the number of vias used for these connections. Up to 2 recommended.

8. High Speed ​​Memory Distribution Routes

Memory allocation is a different story. DDR2 +, QDR, RDRAM, XDR, and other high-speed chips are managed with some very important rules:

  1. The clock line must always be longer than the RAS, CAS and Data lines. The clock must arrive later than the individual signals, otherwise synchronization problems will occur. The high-speed memory controller is usually a & # 39; the clock tracker returned to the controller, so the controller can tell when the chip received the clock.
  2. Data lines can never cross any plane division, as these lines are more active than any other connection in the system.
  3. DDR systems have special elimination requirements (usually voltage cut). This voltage, which is half the memory voltage of the memories, should be very stable, as this section provides endpoint resistances at the end of each line. This power supply must have adequate power management and many capacitor disconnections (10nF on every 4 recommended lines).

For further information, contact the manufacturer's data sheet.

We are now ready and I hope this article has helped to make things clearer in high-speed PCB routing techniques. This article continues in PCB Routing Tips and Tactics 2.

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